1. Field of the Invention
The present invention relates to pipelined semiconductor devices suitable for ultra large scale integration (ULSI), such as pipelined data processing devices, pipelined memory devices, and the like.
2. Description of the Related Art
Pipeline control is widely used for data processing devices typically microprocessors, and memory devices, in order to speed up the operation. An example of a pipelined microprocessor is disclosed for example in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-19, No. 5, October, 1984, at pp. 682 to 689. An example of a pipelined memory is disclosed for example in ISSCC 87 February, 1987, at pp. 256 to 257.
FIG. 23 shows the general structure of a prior art pipelined data processing device. In FIG. 23, reference numeral 2300 represents a data processing device having functional blocks 2310 and 2320. The functional block 2310 has an input latch 2311 and a functional circuit unit 2312. The functional block 2320 has an input latch 2321 and a functional circuit unit 2322. The functional blocks 2310 and 2320 are interconnected by a signal transmission line 240 whose equivalent circuit model is represented by a wiring resistor 241 and a wiring capacitor 242.
FIG. 24 illustrates the pipeline operation of the data processing device shown in FIG. 23. In FIG. 24, a character "A" stands for a clock cycle during which the process by the functional block 2310 and the signal transmission by the signal transmission line 240 are executed. A character "B" stands for a clock cycle during which the process by the functional block 2320 is executed. The characteristic feature common in conventional techniques is that the process time "A" contains not only the process time of the functional block 2310 but also the signal transmission time by the signal transmission line 240.
FIG. 25 shows a typical chip layout of a general semiconductor memory device. In FIG. 25, reference numeral 2500 represents a chip of the semiconductor memory device. Reference numerals 2510-1 to 2510-8 represent memory arrays. Reference numerals 2520-1 to 2520-7 represent address decoders. Reference numerals 2530-1 to 2530-8 represent inner peripheral circuits each including a column select switch, a sense amplifier, and the like. Reference numerals 2540-1 and 2540-2 represent pad areas. Reference numeral 2550-1 represents an outer peripheral circuit including an address input circuit. Reference numeral 2550-2 represents an outer peripheral circuit including an output driver circuit. A signal line 2560 supplies an address signal from the peripheral circuit 2550-1 to the address decoders 2520-1 to 2520-7, and is a long wiring extending in the longitudinal direction of the chip 2500. Another signal line 2570 transfers a signal between the inner peripheral circuits 2530-1 to 2530-8 and the outer peripheral circuit 2550-2, and is also a long wiring extending in the longitudinal direction of the chip 2500. In the pipeline operation of the semiconductor memory device having such long wirings, one pipeline cycle contains both the process time by the functional circuit unit and the signal transmission time by the signal line 2560 or 2570, similar to the data processing device described above.
A significant issue with the above-described conventional technique is that one pipeline cycle contains not only the process time by the functional circuit unit which varies depending upon a device performance and circuit configuration, but also the signal transmission time which varies depending on the material, structure, and length of the wiring. The performance of the functional circuit unit can be improved through introduction of a high performance device due to the advancement of fine processing technique, and high speed circuit configuration. On the other hand, however, wiring resistance and capacitance increase as the fine processing technique advances, lengthening the signal transmission time. Accordingly, the pipeline cycle cannot be shortened to the extent as expected, but to make matters worse, the pipeline cycle is required to be lengthened.
FIG. 26 is a graph illustratively showing how an increase in the signal transmission time on a wiring becomes a serious obstacle against realizing a future high speed ULSI semiconductor device, when a conventional pipeline operation is applied. In FIG. 26, it is assumed that in the fine processing generation SO, the operation frequency is 33 MHz, the circuit delay time is 27.9 ns, and the wiring delay time is 2.1 ns, and that the circuit performance is improved by 150% in each new generation through scaling and the wiring delay time increases by 150% in each new generation in a conservative estimate.
The solid line curve of FIG. 26 shows an ideal operation frequency to be expected from an improved device performance caused by the advancement of fine processing technique, without considering the wiring delay time. The broken line curve of FIG. 26 shows an operation frequency to be expected when considering the wiring delay time. As seen from FIG. 26, in the ideal case neglecting the wiring delay time, the operation frequency can be speeded up to about 270 MHz in the generation S5. However, when considering the wiring delay time, the operation frequency is improved only by two times over three generations from the generation S0 with 33 MHz to the generation S3 with a peak operation frequency of about 65 MHz. Starting from the generation S4 with much advanced fine processing technique, the operation frequency decreases. In the next generation S5, only the operation frequency of about 51 MHz can be realized which is about one fifth the ideal case. The following solutions to the above-described wiring delay problem are conceivable:
(1) Use of wide wiring and a buffer having a high speed and large load driving capability.
(2) Development of a new wiring material providing small resistance and capacitance.
(3) Development of a new layout providing short wiring, such as three-dimensional layout.
(4) Improvement of a system providing a short wiring.
Although the solution (1) can be practiced, the high integration of an ULSI chip is sacrificed, and so this solution (1) cannot be used in practice. The solutions (2) and (3) require a possible long term for research and development. These techniques have not been established as yet. For the solution (4), a particular and fundamental means is not still realized. A circuit layout design for minimizing a signal delay of a wiring has been proposed in U.S. Ser. No. 07/630,553 filed on Dec. 20, 1990 and assigned to the present assignee, which is incorporated herein by reference.